The High-Speed Channels (HSC) provide routes to the host that can be used to transfer data between the PC and the DSP at rates that are considerably greater than can be achieved using the host comport link.
The HSC provides eight channels using a mechanism based on three features of Sundance carrier boards:
1. |
Mailboxes, which allow interrupt-driven communication of single 32-bit words between the host and the root processor. |
2. |
SRAM, which is an area of shared memory that can be directly accessed by the PC and indirectly accessed by the DSP; and |
3. |
PCI access, which allows data transmission between the DSP memory and locked-down memory area on the host. In order to do this, the DSP needs to have a definition of where the PC has locked the memory. The PC provides this information as a Memory Descriptor List (MDL) that is written to part of the SRAM. The MDL for a channel is initialised on an OpenPci function call and not be altered until the memory is released by a ClosePci call. Between these calls, the DSP is free to cache information about the host's memory. |
References to a particular high-speed channel must be sequential. You may not have one thread reading from a channel while another thread is writing to the same channel. It is safe to access different channels at the same time.