The VHDL files produced by System Generator may be synthesized with XST to produce a netlist.
The netlist generated must not have any I/O buffers, since the task will be used in a higher level design. In most cases it shouldn’t implement any clock buffers since Diamond implements them for you. The configuration XST is shown below. Add I/O buffers must not be ticked; all the other options can be set to values you choose.
