Keyword

Meaning

PROCESSOR

identifies the FPGA processor on which the clock is being defined. This field is omitted when a clock is defined within a PROCTYPE.

SOURCE

identifies a signal that used to derive the new clock. This may be the name of an existing clock domain, the name of a task on the FPGA that generates a clock signal, or the name of a pin (or a pair of pins for a differential clock).

Clock domains defined inside a PROCTYPE cannot be derived from a task.

A task that is used as the source for a clock domain must provide the port Clk_out. To minimize the chances of problems, we recommend that you do not cascade more than two clock domains.

INPUT

gives the frequency of the input clock. You can omit this if the frequency of the clock source is known to the system (for example, if the clock is derived from another clock); if you do give it, it must match the clock source frequency.

It is an error to omit this field if the frequency of the clock source is unknown.

OUTPUT

is the rate at which the clock is to tick. This is the same as the frequency defined for a pin or is derived from another clock, in which case Diamond automatically synthesizes the correct clock.

STANDARD

is the electrical standard to which a clock connected to the pins of the FPGA conforms (LVTTL, LVPECL,...). This optional parameter is not used when one clock domain is derived from another.