Simulating an FPGA Attached to a DSP

A DSP communicates with the FPGA to which it is attached via its EMIF.

When simulating an FPGA attached to a DSP, we suggest you create a testbench that instantiates the FPGA and connects it to a ProgramDsp component via the DSP I/Os.

The ProgramDsp component simulates the program running on the DSP and stimulates the FPGA using the I/Os signals that are normally driven by the EMIF.

When a DSP task is connected to an FPGA task, Diamond implements communication resources in the FPGA and loads device drivers in the DSP to manage the communication.

There are 3 types of communication resource that Diamond uses:

Simulation models are provided with Diamond to simulate the DSP drivers and the IP cores used in the FPGA, and these can be found in package dsp_device_drivers_pkg compiled in library diamond, found in the folder <3L>Diamond\edition\Sundance\Xilinx\src\Simulation.

You need to look in the top.vhd file created by Diamond to determine which communication resource is used to communicate with your tasks.  This process should be automated in future versions of Diamond.

The following code snippet shows an example of a ProgramDsp component that writes and reads a few words to the FPGA using functions WriteRsl() and ReadRsl().

Note the following code is module-dependent:

       dspa.i.dsp_name   <= smt395;

You must replace smt395 by the board you are using as defined in dsp_model_pkg, compiled in library diamond.

library ieee;

use ieee.std_logic_1164.all;

use IEEE.NUMERIC_STD.all;

use work.dsp_model_pkg.all;

use work.dsp_device_drivers_pkg.all;

library diamond;

use diamond.chan_pkg.all; 

library Smt;

use Smt.Smt_pkg.all; 

use work.diamond_pkg.all;

use work.txt_util.all;

entity  ProgramDsp is

  port (

    clk : inout std_logic;

    rst : in std_logic;

    o_DSP0 : out t_Dsp_PB_X;

    i_DSP0 : in t_Dsp_PB_Y;

    io_ed_DSP0 : inout std_logic_vector (31 DOWNTO 0)

   );

end ProgramDsp;

architecture behav_ProgramDsp of ProgramDsp is

signal dspa : dsp_sim;

signal clock: std_logic;

begin

   dspa.i.dsp_name   <= smt395;

   --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

   -- Always keep the following statements 

   --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

   clk_generate(dsp_list(dspa.i.dsp_name).period, clock);  

   dspa.i.clk        <=  clock;

   dspa.i.ardy       <= '1';

   dspa.i.nrst       <= not rst;      

   o_DSP0.ncas            <= dspa.o.ncas; 

   o_DSP0.ea            <= dspa.o.ea(o_DSP0.ea'range);

   o_DSP0.nbe            <= dspa.o.nbe;

   o_DSP0.nce(3)     <= dspa.o.nce3;

   o_DSP0.nras            <= dspa.o.nras;

   o_DSP0.nwe            <= dspa.o.nwe;

   dspa.i.i_ed            <= io_ed_DSP0;         -- bidir data bus

   io_ed_DSP0        <= ouput_tri(dspa.o.o_ed, dspa.o.t_ed);     

   --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

   clk                      <= transport dspa.i.clk after 5ns; -- to have the control signals in 

                                                        -- the middle of the clock

P_Program : process

       variable data: integer;        

   variable e: boolean := false; 

begin  

  wait until rst='0';

  wait until rising_edge(dspa.i.clk);

  init(dspa.o,dspa.i); -- initialises the simulation model

       for i in 16#61# to 16#7A# loop

      WriteRsl (dspa.o, dspa.i, i, 1);

       end loop;    

       for i in 0 to 15 loop

      ReadRsl (dspa.o, dspa.i, data, 1);

      print("Result is 0x" & hstr(std_logic_vector(to_unsigned(data, 8))));  

       end loop;    

       wait;

end process;      

end behav_ProgramDsp;