Resource

Use

Internal memory

The kernel often occupies part of internal memory; you can find out where it has been placed by examining the listing file generated by 3L A option -l. Optimizing the placement of sections of tasks or enabling the cache may move the kernel into different parts of the available memory, internal or external.

EDMA

Diamond dynamically assigns DMA channels DMA4–DMA7 to operations using Sundance peripherals (SDBs, for example). If a new concurrent I/O operation is started and no suitable DMA channel is free, CPU interrupts are used for the transfer until one of the necessary DMA channel is released (whereupon that channel is claimed by an active I/O operation that does not have one).

Any number of concurrent link I/O operations can be handled in this way.

This dynamic assignment of DMA channels to I/O operations means that if you want to control a DMA channel directly, you must explicitly claim it from the kernel using the DMA functions.

INT4, INT5, INT6

These interrupts are connected to the FPGA to which the DSP is attached and are used by Diamond to control I/O between the DSP and the FPGA. If you need to use one of these interrupts directly, you must explicitly claim the interrupt line from the kernel by first calling one of the EXT_INT functions.

INT7

INT7 is also connected to the FPGA but this interrupt is permanently reserved for handling devices when no free DMA channels are available.

INT14 (timer 0)

Reserved. The kernel initializes timer 0 to interrupt once every millisecond. These interrupts support task time-slicing and the timer.h functions. To minimize overheads, the kernel handles the timer 0 interrupt specially; you cannot attach your own handler to it.

INTMUXn registers

The INTMUX registers are used to map a selection of the large number of events provided by the C64 processors onto the small number (12) of available CPU interrupts. Diamond sets these registers during system initialisation to allow various devices to be managed. Please contact 3L if you wish to map new events onto CPU interrupts, as careless modification of the INTMUX registers can easily lead to obscure system failures.