Required Signals

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System Generator automatically adds the following ports for you if there is at least one synchronous element in the task. If your processing is purely asynchronous you can add a register on the validwords signal to force system generator to implement these ports.


clk

ce

rst

Port ce_clr is not added by System Generator.  You should add an input gateway to your model called 'ce_clr' to ensure this signal is present on the interface on the core created by System Generator.