Register Block

This device provides three memory mapped registers to the DSP. The registers can be read and written by the DSP and any task in the FPGA.

There is no synchronization between the register ports of this device and the task(s) they are connected to. If they are not in the same clock domain there will be data loss. This core should only be used if this is not a problem. Otherwise, you should use channels between tasks instead of this device.

You can read and write the registers from any task running on the DSP associated with the device. The offset from the base address of the FPGA is described in the table below.

	Register	DSP Offset
	Register #0	0x001A4000
	Register #1	0x001A4004
	Register #2	0x001A4008

FPGA tasks can read and write the registers by declaring ports with on its entity as described in the table below.

	Register	FPGA Task Port Declaration
	Register #0	DEVICE_custom_register_dsp$_PORT_register0_x: in std_logic_vector(31 downto 0); DEVICE_custom_register_dsp$_PORT_register0_y: out std_logic_vector(31 downto 0);
	Register #1	DEVICE_custom_register_dsp$_PORT_register1_x: in std_logic_vector(31 downto 0); DEVICE_custom_register_dsp$_PORT_register1_y: out std_logic_vector(31 downto 0);
	Register #2	DEVICE_custom_register_dsp$_PORT_register2_x: in std_logic_vector(31 downto 0); DEVICE_custom_register_dsp$_PORT_register2_y: out std_logic_vector(31 downto 0);