Performance

Any performance figures quoted for link devices are maxima; the actual rates achieved in practice depend on several things:

•	The size of the transfer. There is a fixed overhead associated with managing any transfer. This overhead becomes negligible when moving large amounts of data, but tends to dominate small transfers.

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Availability of DMA. When you start a transfer,the kernel attempt to allocate a DMA channel to manage moving the data. The number of DMA channels available is limited to three. There are only four external interrupt lines and one needs to be used to synchronise each DMA transfer. One of these lines must be reserved to act as a fallback for transfers that cannot use DMA and must be managed with CPU interrupts. If all available DMA channels are tied up with concurrent transfers or have been claimed for other uses in the application, the transfer have to use CPU interrupts and achieve a considerably reduced transfer rate.

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The alignment of the data. Because of the inability of the C6000 DMA to maintain coherency between the cache and external memory, the Diamond kernel has to limit the use of DMA to transfers or sections of transfers that are aligned on a cache-line boundary (addresses which are a multiple of 128) and of a size that is a multiple of the cache-line size (128 bytes). Parts of a transfer that are misaligned or not a multiple of 128 bytes are handled by CPU interrupts, and this is considerably slower than using DMA.

The configurer normally choose the links to be used to carry channels created by CONNECT statements. If you need a connection to use a particular wire, for example, to make sure it uses a fast SDB link or a slower comport link, you should explicitly PLACE the connection on the wire. For example: