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Diamond works with the Aldec Active-HDL simulation tool to allow you to simulate your Diamond FPGA applications.
Diamond creates an Active-HDL script for each FPGA in your application. The scripts are created in the 'temp_bldx' folder corresponding to each FPGA. These can be used to simulate the individual HDL tasks or the whole FPGA.
The following scripts are created:
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AldecAhdl_prj_FrameworkFpga.do
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running this script creates the Active-HDL project with all the files you may need for the simulation
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AldecAhdl_BuildSrc_FrameworkFpga.do
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running this script compiles the HDL files in the relevant libraries
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AldecAhdl_prj_FrameworkFpga.bat
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this batch file contains the command line to create the Active-HDL project
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You should follow these steps to create a simulation project:
1.
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Build your Diamond application.
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2.
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Go to the temp_bldx folder that corresponds to the FPGA you wish to simulate and copy the file AldecAhdl_prj_FrameworkFpga.bat to the directory where you wish to create the simulation project.
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3.
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Run AldecAhdl_prj_FrameworkFpga.bat by double clicking it. This launches Active-HDL and creates the project. The time this process takes depends on the number of files in your tasks.
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4.
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In Active-HDL, run AldecAhdl_BuildSrc_FrameworkFpga.do to compile the sources.
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