The Addone example is the simplest of Diamond FPGA applications. It uses an attached FPGA to add one to a value. The main program generates and sends data to the add-one task in the FPGA and the results are sent to the output area.
The diagram shows the two tasks used in the example. Task driver generates a counter that it sends to task addone. Task addone increments each value by one and sends the result back to driver. Task driver prints the original values and the results.
Running the Example
Make sure you have set the default processor type corresponding to the hardware you have as explained here.
You can build the application by typing Ctrl+B and then execute it by clicking run. Note that building this application takes a few minutes as it involves launching the Xilinx tools.
We have provided two implementations for task addone:
C |
used when the addone task is placed on a DSP |
|
VHDL |
used when the addone task is placed on an FPGA |
Because you have these two implementations, you can move the addone task from the FPGA to the DSP by dragging and dropping. Press run to re-build and execute the modified example.
Prerequisites
You need the following components to be able to run this example:
Hardware |
Quantity |
|
At least one DSP and one FPGA |
- |
|
3L Diamond DSP licence |
1 |
|
3L Diamond FPGA licence |
1 |