Default Clock Domains

The default clock of a DSP module is the clock of its root DSP's EMIF. The user manual of the board should provide the frequency of this clock. For an FPGA only module, the default clock usually comes from an oscillator on the board. The table below shows for each FPGA module supported by Diamond the frequency of its default clock.

Processor type	Frequency (Mhz)
SMT148FX_FX60	50
SMT148FX_S1500	48
SMT318_SX55_F1_12	50
SMT318_SX55_F2_12	50
SMT338_VP30	125
SMT348_LX160	50
SMT348_LX160	50
SMT349	50
SMT351_VP7	125
SMT351_VP30	125
SMT351T	50
SMT368_SX35	50
SMT368_SX35_12	50
SMT368A_SX35	50
SMT370	50
SMT377	50
SMT398_V8000	50
SMT398_V6000	50
SMT398_VP50	50
SMT398_VP70	50