This example shows a simple addone task designed in Verilog.
A task called 'addone_verilog' is created in the Diamond IDE. File addone_verilog.vhd is deleted. It will be implemented in Verilog and synthesized outside the IDE. The resulting netlist 'addone_verilog.ngc' will be imported in the IDE.
File addone_verilog is shown below:
`timescale 1ns / 1ps
module addone_verilog(clk, rst, ce, ce_clr,
x_chan_in_0_write, x_chan_in_0_data, x_chan_in_0_validwords, y_chan_in_0_ready,
x_chan_out_0_write, x_chan_out_0_data, x_chan_out_0_validwords, y_chan_out_0_ready,
);
input clk;
input rst;
input ce;
input ce_clr;
input x_chan_in_0_write;
input [63:0] x_chan_in_0_data;
input [1:0] x_chan_in_0_validwords;
output y_chan_in_0_ready;
output x_chan_out_0_write;
output [63:0] x_chan_out_0_data;
output [1:0] x_chan_out_0_validwords;
input y_chan_out_0_ready;
assign y_chan_in_0_ready = y_chan_out_0_ready;
assign x_chan_out_0_write = x_chan_in_0_write;
assign x_chan_out_0_data = x_chan_in_0_data + 1;
assign x_chan_out_0_validwords = x_chan_in_0_validwords;
endmodule
addone_verilog.v is synthesised with the option 'Add I/O Buffers' deselected:
