Verilog

Diamond allows you to develop tasks in VHDL. There is no direct support for Verilog. Here is a method you can follow if you want to design tasks using the Verilog language.

The Verilog components used in your tasks must be synthesized separately using the Xilinx ISE flow.  The resulting netlists are imported in the Diamond environment.

Diamond tasks communicate with each other using channels.  Each channel is constructed from two buses, X and Y, going in opposite directions.  In VHDL we defined the following two types to gather the signals of each one of the buses:

These types do not exist in the Verilog language.  Instead, in Verilog channels are defined as follow.

An input channel:

input x_chan_in_x_write;

input [63:0] x_chan_in_x_data;

input [1:0] x_chan_in_x_validwords;

output y_chan_in_x_ready;

An output channel:

output x_chan_out_x_write;

output [63:0] x_chan_out_x_data;

output [1:0] x_chan_out_x_validwords;

input y_chan_out_x_ready;

where 'x' is the number of the channel.