The logic generated by Diamond for an FPGA is built within a 'framework component' that has fixed functionality for given hardware and cannot be changed. For example, the framework may implement a memory controller giving access to memory chips connected to the FPGA, or it may provide an interface to a DSP attached to the FPGA. The functionality of the framework depends on the hardware targeted and is described in the vendor-specific section of this document.
The framework contains a 'Top' VHDL block inside which Diamond creates the FPGA tasks and communication links required by your application.
The framework connects to pins of the FPGA. Some pins are connected directly to the top component and some are connected to it through logic blocks (cores). You may access these pins (or cores connected to pins) explicitly from your FPGA tasks or implicitly via communication links. Other FPGA pins may be attached to cores that are not connected to the top component.
Tasks can access the resources of the framework that are connected to the Top component, for example, a task may connect to a memory controller implemented in the framework. You make connections to the framework resources by adding ports to your FPGA tasks which must have specific names, types and directions, and these are described in the vendor-specific section of this document.
When Diamond sees these ports in your task's entity, it connects the task to the relevant resources in the framework. The majority of these resources can be used by one task only.
