The following diagram shows how the various signals are used to transfer 32-bit data across a channel; the convention is that signals are asserted high.
In the initial state, the receiver is ready to accept data and so has asserted Ready, while the transmitter has set ValidWords to 012 indicating it is transferring 32-bit words.
At clock cycle 2, the transmitter decides to send three 32-bit words: D0, D1, and D2. Seeing that Ready is asserted, the transmitter places D0 on Data and asserts Write.
The receiver, on seeing Write asserted, determines that it does not yet wish to receive any more words after D0 and so deasserts Ready at the next rising clock edge (cycle 3). This edge also independently causes D0 to be received. The transmitter, eventually seeing that Ready is no longer asserted, deasserts Write before the next rising clock edge (cycle 4).
A few cycles later, the receiver decides to accept more words and once again asserts Ready. The transmitter responds by placing the next word, D1, on Data and asserting Write. The data are transferred on the next rising clock edge (cycle 7). The transmitter sees this rising edge and, as Ready is still asserted, leaves Write asserted and puts D2 on Data.
D2 is transferred on the rising edge of clock cycle 8, at which point the transmitter, having nothing more to send, deasserts Write. It does this even though the receiver is holding Ready asserted to indicate it could receive more data.