Timing Constraints Syntax

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Timing constraints can be entered in a UCF or an XCF file. The appropriate syntax for entering constraints in these files is described in the Xilinx Constraint Guide.

Diamond automatically generates some of the HDL used to build the FPGA, for example, the top level file containing your task and the clock managers providing the clock to your tasks. Diamond defines some special keywords that you can use to refer to these objects in a task's UCF file; they are replaced at compile time with the appropriate strings or values.

The following list describes the supported keywords:

Keyword	Definition	Example of usage
%CLOCKIN%	replaced by the name of the pin providing the task's clock.	OFFSET = IN 5.1ns BEFORE %CLOCKIN%;
%PATH%	replaced by the hierarchical path to the task. For example "i_top\INST0_mytask".	INST "%PATH%_reg0" LOC="SLICE_X95Y52" ;
%CLOCKOUTPERIOD%	replaced by the numerical period of the clock domain in which the task has been placed.	TIMESPEC "TS_1" = PERIOD "TNM_mysig" %CLOCKOUTPERIOD%;