When a DSP and an FPGA are attached, they communicate via the EMIF interface of the DSP. Although the C64 series of DSP has a 64-bit EMIF, the interface that is implemented by Diamond is always 32 bits. It is not possible to use the 64 bits of the EMIF bus. When an FPGA task transmits to a DSP task, the 32-bit words to send should be placed on the lower 32 bits of the channel between them; data located on the upper 32 bits is discarded. Similarly when an FPGA task receives from a DSP task, the 32-bit word it receives is located on the lower 32 bits of the channel.