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The term ports in this context are not connection points for channels, but ports in the VHDL sense.
Each task must provide the following ports of type std_logic:
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clk
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signals associated with the channels of the task are synchronous to this clock.
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rst
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the signal used to reset the task
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ce
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clock enable. This is not currently used.
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ce_clr
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clock enable clear signal. This is not currently used.
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Optionally, a task may generate a std_logic port that other tasks can use as a clock.
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clk_out
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an optional signal that can be used to derive other clock domains. This signal must be present for any task that is used as the source of a CLOCK in your configuration file.
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