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| • | Compilation must be set to 'HDL netlist'. |
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| • | Part must be set to the FPGA type you are targeting. |
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| • | Synthesis Tool must be set to XST. |
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| • | Hardware Description Language must be set to VHDL. |
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| • | FPGA Clock Period (ns) must be the frequency at which the task is clocked. This setting is overwritten by Diamond with the frequency of the clock domain to which the task belongs. |
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| • | Clock Pin Location must be left unspecified. Diamond connects the clock to the task according to the clock domain specified in the configuration file. |
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