Synchronization Between Clock Domains

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Some sort of synchronization is required when data flows between two components that belong to different clock domains. This can be tricky, as errors will result in data loss or metastability. Diamond deals with this problem automatically by detecting the borders between clock domains and arranging the appropriate synchronization. This is usually done by inserting a memory component in the path, with data being clocked in by one clock and clocked out by the other. In the case of channels, it is possible to inhibit the inclusion of synchronizing logic by marking the channel as NoSync in the FCD file or in the IDE.

 

FPGA_NoSync