Signal Master Quad Virtex 4

The diagram shows a SignalMaster Quad with the connections provided by the default firmware shown in black. Links between DSP devices 1 and 2 and devices 3 and 4 are used automatically to implement channels you declare between tasks on those pairs of DSPs.

DSP1 and DSP3 have access to RCH_FPL:0 through their respective DRC boards.

DSP1 and DSP3 are connected via RCH_INT:0.

There are four FastBus connections available between the two DSPs on each cluster.

Each FPGA has an RCH_INT:0 link that corresponds to the on-board link between the two FPGAs; this link must be declared as a WIRE if you wish to use it. The processors accessing the connector should be those that need to use the link. For example, if you want a task on DSP1 to be able to use the internal connector to communicate with DSP4, you would use the following:

PROCESSOR FPGA1 SMQ_LX100_FPGA BOARD=0 DEVICE=1

PROCESSOR FPGA2 SMQ_LX100_FPGA BOARD=0 DEVICE=2

PROCESSOR DSP1  SMQ_DSP        BOARD=0 DEVICE=1 ATTACH=FPGA1

PROCESSOR DSP4  SMQ_DSP        BOARD=0 DEVICE=4 ATTACH=FPGA2

WIRE W1 L_DSP1[RCH_INT:0] DSP4[RCH_INT:0]

If, instead, you wanted a task on FPGA 1 to communicate with a task on DSP3, you would use this:

PROCESSOR FPGA1 SMQ_LX100_FPGA BOARD=0 DEVICE=1

PROCESSOR FPGA2 SMQ_LX100_FPGA BOARD=0 DEVICE=2

PROCESSOR DSP3  SMQ_DSP        BOARD=0 DEVICE=3 ATTACH=FPGA2

WIRE W1 FPGA1[RCH_INT:0] DSP3[RCH_INT:0]

Consider the following statement, which assumes the processor declarations above:

WIRE W1 FPGA1[RCH_INT:0] FPGA2[RCH_INT:0]

This reserves the links for use by the respective FPGAs; none of the DSPs would have access to them.

The following links are available for WIRE statements: