This section describes how Diamond implements clock domains in an FPGA.
Derived from a task
Diamond connects the task's output signal clk_out directly to the tasks or devices placed in this clock domain. No extra logic is added.
You must explicitly create a period constraint for the clock in the task as it is not generated automatically.
Derived from pins
Diamond connects the pins to a global clock buffer and connects the output of the buffer to the tasks and devices placed in the clock domain. A clock period constraint is generated automatically.
Derived from another clock domain
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When Diamond uses a DCM to implement a clock domain, the clock of the tasks placed in the clock domain will be stable after the reset of the task has been de-asserted. If your task also uses a DCM you need to include a circuit in the task to reset the DCM until it locks.
Similarly, you should ensure that the input clock of a domain that uses a DCM is a continuous signal that is always present. If this is not the case, the DCM lock will be lost and the output clock will not be stable.