Several options become available when a task has been placed on an FPGA. Double-click the task to bring up the task edit pane.
Task format defines how an FPGA task is being described. You can change to other options by clicking Select.
Task options/General allows you to mark the task as being stand alone.
Advanced options provide control over the way in which an FPGA task is built.
Clock domain allows you to specify the clock that is used for this task. Note that this option is presented only if you have defined clock domains for the processor on which the task has been placed.
Pre-compile to netlists allows you to build applications faster by caching information for a task rather than constructing it each time the application is built. When this option is ticked, the IDE looks for a netlist file corresponding to this task; a new one is built if one cannot be found or it is out of date with respect to the task source files. Any existing, current netlist is incorporated into the bitstream for the processor without rebuilding.
Refer to the Xilinx documentation for a description of the items that can be found under Build options for Xilinx.