Diamond organizes components on an FPGA as tasks; your blocks of logic are built as tasks and so are the FPGA's devices. These tasks have input and output ports that can be connected with channels in the usual way, and, just like all other tasks in Diamond, you can give them as many input and output ports as you choose, but if you give a task no ports at all, it will not be able to communicate with other tasks.
Unlike CPU tasks which have a certain flexibility, FPGA tasks involve setting programmable logic into a particular configuration that is fixed when the task is constructed. It follows that all instances of any particular task must have the same numbers of input and output ports.
A channel's unidirectional data transfer is achieved using two buses, X and Y, which carry signals in opposite directions between the communicating tasks. Each task always sees the signals of the channels it can access as being synchronous to its own clock. Diamond arranges for this to be true even if you should use a channel to connect tasks that have different clocks. Clocks are discussed later.
The transmitting task drives the X bus to send data to the receiver using these signals:
Write |
asserted high to start a write operation. Information on the data bus (Data) will be read by the receiver on the next rising clock edge when Write is asserted. |
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Data |
64-bit data. This is considered to be two 32-bit words; one or both may be valid depending on the state of ValidWords (see below). |
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ValidWords |
describes which of the 32-bit data words are valid.
Other values of ValidWords are undefined and must not be used. |
The receiving task drives the Y bus's only signal, Ready, to tell the sender whether it is ready or not to receive data. A transmitter must wait until the receiver's ready signal is asserted before it asserts Write:
Ready |
asserted high to indicate that the transmitter may send data. |
These two busses are defined by VHDL types, declared in the package file chan_pkg.
type X_chan_t is record
data : std_logic_vector (63 downto 0);
write : std_logic;
validwords : std_logic_vector (1 downto 0);
end record
type Y_chan_t is record
ready : std_logic;
end record
This package file has been compiled in the library diamond. You include it in your task as follows:
library diamond;
use diamond.chan_pkg.all;