Lyrtech boards use FPGAs to implement a high-speed communication mechanism called FastBus. The actual connections made by the FastBus links vary depending on how the FPGAs have been configured and what daughter modules are present. These links are normally invisible to you. Diamond manages their use automatically.
Each FPGA has access to two connectors that can be used with FastBus links.
RCH_FPL:0 |
an external connector controlled by a DRC module. |
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RCH_INT:0 |
an internal connector used to communicate between two FPGAs on one SignalMaster Quad board or two SignalMaster Dual boards. |
There are actually two sets of these links within a SignalMaster Quad, one set for each cluster. Within a cluster, either DSP has the potential to be given access to these links, but each link can actually be connected to one DSP only.
The diagram shows a SignalMaster Quad with the default connections (shown in black). Using different connections from these leads to the creation of one or more new FPGA or DRC bitstreams. Links between DSP devices 1 and 2 and devices 3 and 4 are used automatically to implement channels you declare between tasks on those pairs of DSPs.
Each FPGA has an RCH_INT:0 link that corresponds to the on-board link between the two FPGAs; this link must be declared as a WIRE if you wish to use it. The processor accessing the connector should be the one that needs to use the link. For example, if you want a task on DSP1 to be able to use the internal connector to communicate with DSP4, you would use the following:
PROCESSOR FPGA1 SMQ_LX100_FPGA BOARD=0 DEVICE=1
PROCESSOR FPGA2 SMQ_LX100_FPGA BOARD=0 DEVICE=2
PROCESSOR DSP1 SMQ_DSP BOARD=0 DEVICE=1 ATTACH=FPGA1
PROCESSOR DSP4 SMQ_DSP BOARD=0 DEVICE=4 ATTACH=FPGA2
WIRE W1 L_DSP1[RCH_INT:0] DSP4[RCH_INT:0]
If, instead, you wanted a task on FPGA1 to communicate with a task on DSP3, you would use this:
PROCESSOR FPGA1 SMQ_LX100_FPGA BOARD=0 DEVICE=1
PROCESSOR FPGA2 SMQ_LX100_FPGA BOARD=0 DEVICE=2
PROCESSOR DSP3 SMQ_DSP BOARD=0 DEVICE=3 ATTACH=FPGA2
WIRE W1 FPGA1[RCH_INT:0] DSP3[RCH_INT:0]
Consider the following statement, which assumes the processor declarations above:
WIRE W1 FPGA1[RCH_INT:0] FPGA2[RCH_INT:0]
This reserves the links for use by the respective FPGAs; the DSPs would have no access to them.
The following links are available for WIRE statements:
DSP1 |
RCH_FPL:0 on FPGA device=1, the front-panel connector connecting to a different board via DRC device=1 |
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RCH_INT:0 on FPGA device=1 connected internally to RCH_INT:0 on FPGA device=2. This link is routed to the front panel on a SignalMaster Dual. |
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DSP2 |
no connectors in default firmware |
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DSP3 |
RCH_FPL:0 on FPGA device=2, the front-panel connector connecting to a different board via DRC device=2 |
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RCH_INT:0 on FPGA device=2 connected internally to RCH_INT:0 on FPGA device=1 |
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DSP4 |
no connectors in default firmware |