Deriving from the default clock
This example creates a 25MHz clock called SlowClock on processor node. It is derived from the default clock on that processor.
CLOCK SlowClock processor=node source=DEFAULT output=25MHz
In the Diamond IDE the same clock domain is defined as follows:
Deriving from another clock domain
This example creates a 50MHz clock called FastClock on processor node. It is derived from clock domain SlowClock created in the previous example.
CLOCK FastClock processor=node source=SlowClock output=50MHz
In the Diamond IDE the same clock domain is defined as follows:
Declaring a new clock
This example declares a 100MHz clock coming from a pair of differential pins of the FPGA.
CLOCK myclk processor=node source="AH16":"AF16" standard=LVPECL_25 input=100MHz output=100MHz
In the Diamond IDE the same clock domain is defined as follows:
