EMIF

Tasks can connect to the Asynchronous EMIF interface implemented in the OPB subsystem.

The following signals should be added to your FPGA task to connect to the EMIF:

emif_clk                       : in std_logic;

emif_ed_in                     : in std_logic_vector(31 downto 0);

emif_aoe_n                     : in std_logic;

emif_are_n                     : in std_logic;

emif_awe_n                     : in std_logic;

emif_be_n                      : in std_logic_vector(3 downto 0);

emif_ea                        : in std_logic_vector(21 downto 2);

custom_logic_sel               : in std_logic;

custom_logic_data              : out std_logic_vector(31 downto 0);

custom_logic_ardy              : out std_logic;