Custom Registers

The DRC provides eight 32-bit general-purpose registers which you can access directly using offsets 0x40 to 0x7C.

The following signals should be added to your FPGA task to connect to the registers:

iv32_HostUserReg0In_p                   : in  std_logic_vector(31 downto 0);

iv32_HostUserReg1In_p                   : in  std_logic_vector(31 downto 0);

iv32_HostUserReg2In_p                   : in  std_logic_vector(31 downto 0);

iv32_HostUserReg3In_p                   : in  std_logic_vector(31 downto 0);

iv32_HostUserReg4In_p                   : in  std_logic_vector(31 downto 0);

iv32_HostUserReg5In_p                   : in  std_logic_vector(31 downto 0);

iv32_HostUserReg6In_p                   : in  std_logic_vector(31 downto 0);

iv32_HostUserReg7In_p                   : in  std_logic_vector(31 downto 0);

ov32_HostUserReg0Out_p                  : out std_logic_vector(31 downto 0);

ov32_HostUserReg1Out_p                  : out std_logic_vector(31 downto 0);

ov32_HostUserReg2Out_p                  : out std_logic_vector(31 downto 0);

ov32_HostUserReg3Out_p                  : out std_logic_vector(31 downto 0);

ov32_HostUserReg4Out_p                  : out std_logic_vector(31 downto 0);

ov32_HostUserReg5Out_p                  : out std_logic_vector(31 downto 0);

ov32_HostUserReg6Out_p                  : out std_logic_vector(31 downto 0);

ov32_HostUserReg7Out_p                  : out std_logic_vector(31 downto 0);

iv8_HostUserRegWrite_p                  : in  std_logic_vector(7 downto 0);

iv8_HostUserRegRead_p                   : in  std_logic_vector(7 downto 0);