Conventions

You must use strict conventions when you specify a task as a VHDL file.

Each channel that you use must be declared as a pair of signals of type X_chan_t and Y_chan_t:

<index> represents the channel number, the only variable part of the name. Both input and output channels are numbered from zero and the channel numbers must be continuous. In other words, if you declare X_chan_in_3, you must also declare X_chan_in_0, X_chan_in_1, and X_chan_in_2.

For example, the following code is the VHDL description of a task named 'my_task'. It has one input channel and two output channels.

entity my_task is

   port (

      clk          :  in std_logic;

      rst          :  in std_logic;

      ce           :  in std_logic;

      ce_Clr       :  in std_logic;

      x_chan_in_0  :  in X_chan_t;

      y_chan_in_0  : out Y_chan_t;

      x_chan_out_0 : out X_chan_t;

      y_chan_out_0 :  in Y_chan_t;

      x_chan_out_1 : out X_chan_t;

      y_chan_out_1 :  in Y_chan_t

   )

end my_task;

architecture rtl of my_task is

begin

   …

end rtl;