Clock domains

Everything in the FPGA is driven by clocks; the tasks and communication devices from which you construct your firmware all need access to clocks. Sometimes different tasks may need to work at different speeds, and so a design can require more than one clock. Tasks and communication devices that all use the same clock are said to belong to a clock domain.

Each FPGA has a number of clocks; the number and frequency of them is system-dependent. Unless you say otherwise, all the FPGA components belong to a single domain that is referred to as the default clock domain and can be referenced in a configuration file with the identifier 'default'.

The default clock of an FPGA connected to a DSP is the clock of the EMIF of the DSP; the frequency of this clock is specified in the user manual for the hardware.

You can create new clock domains in the FPGA with the characteristics you require and then associate tasks and devices with them. Diamond synthesises the clocks and connects them to the appropriate parts of the firmware automatically.