All C6000 family processors have a two-level cache scheme. This facility is usually (but not always) a net benefit for many applications that are too large to fit entirely into the processor’s internal memory. The L1 cache uses a private memory area within the processor and is always enabled. The L2 cache uses some or all of the processor’s internal memory to hold cache information. Following reset, the L2 cache is configured to use no internal memory, and so is disabled.
The cache mechanism is always used for internal memory and its operation there is effectively invisible to the running program.
Use of the cache (both L1 and L2) with external memory is optional and has potential serious problems. Cache operation with external memory is not invisible to the running program because the cache is unable to maintain coherency with DMA operations. A DMA channel can alter the contents of memory that is being cached. Subsequent program accesses will be satisfied from the cache and so get the old memory contents. Coherency must be maintained explicitly in software by the application. This can be expensive and sometimes reduces performance more than simply disabling the cache.
External memory is divided into a number of areas and each area has an associated Memory Attribute Register (MAR). As part of reset, all MARs are given values that prevent the cache from operating with the corresponding external memory area. This is particularly important in preventing the cache from interfering with the operation of memory-mapped peripherals. During program execution, preferably during the program’s initialisation phase, individual MARs can be set to allow the cache to operate on the selected memory area. Diamond automatically enables the cache by setting every MAR that corresponds to external memory defined by the selected processor type. The setting of selected memory attribute registers can be inhibited using the UNCACHED processor attribute. Diamond's device drivers handle the cache coherency problem for you. If you write your own DMA code, you will need to take action to ensure that coherency is explicitly managed.
The CACHE= attribute of the PROCESSOR declaration allows you to control the amount of internal memory used for L2 cache. The default state, with no internal memory being used for cache, is equivalent to specifying the attribute CACHE=OFF. Conversely, you can use CACHE=ON to indicate that the maximum amount of internal memory should be taken for L2 cache. For finer control, the CACHE= attribute may be supplied with a numeric argument explicitly giving the amount of internal memory to be used for L2 cache; only certain numeric values are permitted for any given processor type. However, CACHE=OFF is always equivalent to CACHE=0 and CACHE=ON is always equivalent to CACHE=x where x is the maximum permitted value. You can find out what values are permitted by looking in the documentation for the particular C6000 processor.